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SM5951A
8-channel DSD Editing System Signal Processor LSI
OVERVIEW
The SM5951A is an 8-channel DSD (Direct Stream Digital) editing system signal processor LSI. It takes 4 DSD input signals per channel, mixes them, and then converts the result back into 1-bit DSD data for output.
FEATURES
I I
I
I
I I I I I I
DSD signal sampling rate: 5.6448MHz (128 x 44.1kHz) and 2.8224MHz (64 x 44.1kHz) supported 8-channel DSD signal mixing * 8-channel, 4 DSD signal inputs per channel mixing using arbitrary coefficients for each input Raw signal switching function (auto bypass) * Automatically switches to raw signal output with no switching noise and no signal degradation when mixing is not required, bypassing the mixing processing Input/output format * Normal input/output format where the data changes are synchronized to the bit clock cycle, and Manchester-type encoding input/output format where the data inverts during the bit clock cycle Monitor output: Simultaneous 64 x 44.1kHz monitor data output when in 128 x 44.1kHz sampling rate mode Microcontroller interface: Parallel bi-directional 8-bit/16-bit/32-bit data bus supported Master clock: 45.1584MHz (1024 x 44.1kHz) or 56.448MHz (1280 x 44.1kHz) 2 voltage supplies: 3.3V (3.0 to 3.6V) and 2.5V (2.3 to 2.7V) Operating temperature range: - 20 to 70C Package: 160-pin QFP
PACKAGE DIMENSIONS
(Unit: mm)
31.2 0.4 28.0 0.1 0.11 to 0.23
28.0 0.1 0.22 to 0.4 3.35 0.1 0.65
31.2 0.4
0 to 10.0 15
1.6
4.0MAX 0.35
15
0.15
0.8 0.8 0.2
ORDERING INFORMATION
Device SM5951AF Package 160-pin QFP
SEIKO NPC CORPORATION --1
SM5951A
BLOCK DIAGRAM
DSDI1_[3:0] DSDI2_[3:0] DSDI3_[3:0] DSDI4_[3:0] DSDI5_[3:0] DSDI6_[3:0] DSDI7_[3:0] DSDI8_[3:0] EXMUTE BCKI SELDSDI
EDIT
DSD_OUT
MIXER_BLK
DSD I/F
(DSD_I/F)
DSD_SW
DSDO [8:1] BCKO
CONV128TO64
CS_X
COEF_GEN
REQ_GEN
RD_X WR_X ADDR [7:0] DATA [31:0] SELBUS [1:0] SEL1280 RST_X FS CLK TEST [8:1]
(DSD64_I/F)
DSD64O [8:1] BCK64O
MCU I/F
SELDSDO
CLOCK GENERATOR & TIMING CONTROL
(Internal Clocks & Control)
MOSYNC
TEST Control
SEIKO NPC CORPORATION --2
SM5951A
PINOUT
(Top view)
VSS DSDI8_3 DSDI8_2 DSDI8_1 DSDI8_0 DSDI7_3 DSDI7_2 DSDI7_1 DSDI7_0 VDDH VSS DSDI6_3 DSDI6_2 DSDI6_1 DSDI6_0 DSDI5_3 DSDI5_2 DSDI5_1 DSDI5_0 VDDL VSS DSDI4_3 DSDI4_2 DSDI4_1 DSDI4_0 DSDI3_3 DSDI3_2 DSDI3_1 DSDI3_0 VDDH VSS DSDI2_3 DSDI2_2 DSDI2_1 DSDI2_0 DSDI1_3 DSDI1_2 DSDI1_1 DSDI1_0 VDDL
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VDDL EXMUTE BCKI FS MOSYNC DATA31 DATA30 DATA29 DATA28 VSS VDDH DATA27 DATA26 DATA25 DATA24 VSS VDDL DATA23 DATA22 DATA21 DATA20 VSS VDDH DATA19 DATA18 DATA17 DATA16 VSS VDDL DATA15 DATA14 DATA13 DATA12 VSS VDDH DATA11 DATA10 DATA9 DATA8 VSS
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VSS SELDSDI SELDSDO VDDH VSS DSD64O8 DSD64O7 DSD64O6 DSD64O5 VDDL VSS DSD64O4 DSD64O3 DSD64O2 DSD64O1 VDDL VSS BCK64O VDDH VSS BCKO VDDL VSS DSDO8 DSDO7 DSDO6 DSDO5 VDDL VSS DSDO4 DSDO3 DSDO2 DSDO1 VDDH VSS TEST8 TEST7 TEST6 TEST5 VDDL
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36
VDDL DATA7 DATA6 DATA5 DATA4 VSS VDDH DATA3 DATA2 DATA1 DATA0 VSS VDDL RST_X SELBUS1 SELBUS0 SEL1280 VSS CLK VDDL ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 VSS VDDH CS_X WR_X RD_X VSS VDDL TEST1 TEST2 TEST3 TEST4 VSS
SEIKO NPC CORPORATION --3
37 38 39 40
1 2 3 4 5 6 7 8 9
SM5951A
Pin Layout Table
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name VDDL DATA7 DATA6 DATA5 DATA4 VSS VDDH DATA3 DATA2 DATA1 DATA0 VSS VDDL RST_X SELBUS1 SELBUS0 SEL1280 VSS CLK VDDL ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 VSS VDDH CS_X WR_X RD_X VSS VDDL TEST1 TEST2 TEST3 TEST4 VSS I/O - I/O I/O I/O I/O - - I/O I/O I/O I/O - - I I I I - I - I I I I I I I I - - I I I - - I I I I - No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name VDDL TEST5 TEST6 TEST7 TEST8 VSS VDDH DSDO1 DSDO2 DSDO3 DSDO4 VSS VDDL DSDO5 DSDO6 DSDO7 DSDO8 VSS VDDL BCKO VSS VDDH BCK64O VSS VDDL DSD64O1 DSD64O2 DSD64O3 DSD64O4 VSS VDDL DSD64O5 DSD64O6 DSD64O7 DSD64O8 VSS VDDH SELDSDO SELDSDI VSS I/O - I I I I - - O O O O - - O O O O - - O - - O - - O O O O - - O O O O - - I I - No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name VDDL DSDI1_0 DSDI1_1 DSDI1_2 DSDI1_3 DSDI2_0 DSDI2_1 DSDI2_2 DSDI2_3 VSS VDDH DSDI3_0 DSDI3_1 DSDI3_2 DSDI3_3 DSDI4_0 DSDI4_1 DSDI4_2 DSDI4_3 VSS VDDL DSDI5_0 DSDI5_1 DSDI5_2 DSDI5_3 DSDI6_0 DSDI6_1 DSDI6_2 DSDI6_3 VSS VDDH DSDI7_0 DSDI7_1 DSDI7_2 DSDI7_3 DSDI8_0 DSDI8_1 DSDI8_2 DSDI8_3 VSS I/O - I I I I I I I I - - I I I I I I I I - - I I I I I I I I - - I I I I I I I I - No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Name VDDL EXMUTE BCKI FS MOSYNC DATA31 DATA30 DATA29 DATA28 VSS VDDH DATA27 DATA26 DATA25 DATA24 VSS VDDL DATA23 DATA22 DATA21 DATA20 VSS VDDH DATA19 DATA18 DATA17 DATA16 VSS VDDL DATA15 DATA14 DATA13 DATA12 VSS VDDH DATA11 DATA10 DATA9 DATA8 VSS I/O - I I I O I/O I/O I/O I/O - - I/O I/O I/O I/O - - I/O I/O I/O I/O - - I/O I/O I/O I/O - - I/O I/O I/O I/O - - I/O I/O I/O I/O -
SEIKO NPC CORPORATION --4
SM5951A
PIN DESCRIPTION
Number of Pins 1 1 1 1 1 1 Name RST_X FS CLK SEL1280 SELDSDI SELDSDO I/O I I I I I I Polarity1 PU, S - - PD, S PD, S PD, S Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V System Reset 1fs Clock (44.1kHz) Master Clock Select Master Clock Rate [HIGH]: 1280 x 44.1kHz, [LOW]: 1024 x 44.1kHz Select DSD Input Format [HIGH]: Manchester Encoding, [LOW]: Normal Select DSD Output Format [HIGH]: Manchester Encoding, [LOW]: Normal Select MCU Data Bus Width [SELBUS1, SELBUS0] [LOW, LOW]: 8-bit [LOW, HIGH]: 16-bit [HIGH, x (LOW or HIGH)]: 32-bit MCU I/F: Chip Select MCU I/F: Write Enable MCU I/F: Read Enable MCU I/F: Address Bus MCU I/F: Data Bus DSD Input: Bit Clock IN DSD Input: DSD CH1 Data (LINE0 to LINE3) DSD Input: DSD CH2 Data (LINE0 to LINE3) DSD Input: DSD CH3 Data (LINE0 to LINE3) DSD Input: DSD CH4 Data (LINE0 to LINE3) DSD Input: DSD CH5 Data (LINE0 to LINE3) DSD Input: DSD CH6 Data (LINE0 to LINE3) DSD Input: DSD CH7 Data (LINE0 to LINE3) DSD Input: DSD CH8 Data (LINE0 to LINE3) DSD Input: External Mute Pattern DSD Output: Bit Clock Out DSD Output: DSD Output DATA (CH1 to CH8) DSD 64fs Output: Bit Clock Out DSD 64fs Output: DSD Output DATA (CH1 to CH8) SYNC Monitor IOTEST_EN, SCAN_EN, ATPG_EN, FUNC_MODE etc. Power Supply (I/O) Power Supply (Core) Ground Level Functional Description
2
SELBUS [1:0]
I
PU, S
3.3V
1 1 1 8 32 1 4 4 4 4 4 4 4 4 1 1 8 1 8 1 8 10 14 24
CS_X WR_X RD_X ADDR [7:0] DATA [31:0] BCKI DSDI1_[3:0] DSDI2_[3:0] DSDI3_[3:0] DSDI4_[3:0] DSDI5_[3:0] DSDI6_[3:0] DSDI7_[3:0] DSDI8_[3:0] EXMUTE BCKO DSDO [8:1] BCK64O DSD64O [8:1] MOSYNC TEST [8:1] VDDH VDDL VSS
I I I I I/O I I I I I I I I I I O O O O O I - - -
PU PU, S PU, S PU 3mA S - - - - - - - - - 6mA 3mA 6mA 3mA 3mA PD - - -
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 2.5V 0V
1. Attributes: S = Schmitt type, PU = with pull-up resistor, PD = with pull-down resistor, mA = output current
SEIKO NPC CORPORATION --5
SM5951A
SPECIFICATIONS
Absolute Maximum Ratings
VSS = 0V
Parameter Supply voltage 1 Supply voltage 2 Input voltage (3.3V) Power dissipation Storage temperature range Symbol VDDH VDDL VIN PD TSTG Rating - 0.3 to 4.0 - 0.3 to 3.0 - 0.3 to VDDH + 0.5 1.3 - 55 to 125 Unit V V V W C
Recommended Operating Conditions
VSS = 0V
Parameter Supply voltage 1 Supply voltage 2 Operating temperature Symbol VDDH VDDL TOPR Rating 3.0 to 3.6 2.3 to 2.7 - 20 to 70 Unit V V C
Electrical Characteristics
DC Characteristics VDDH = 3.0 to 3.6V, VDDL = 2.3 to 2.7V, VSS = 0V, TOPR = - 20 to 70C, unless otherwise noted
Parameter Current consumption 1 Current consumption 2 Input voltage Schmitt trigger voltage Hysteresis voltage HIGH-level Output voltage LOW-level Input leakage current Pull-down resistance Pull-up resistance HIGH-level holding current LOW-level holding current HIGH-level reverse current LOW-level reverse current (*3) (*1) (*2) (*4) (*5) (*6) (*6) (*6) (*6) VOL ILI RPD RPU IBHH IBHL IBHHO IBHLO VI = VDDH VI = VSS VIN = 2.0V, VDDH = 3.0V VIN = 0.8V, VDDH = 3.0V VIN = 0.8V, VDDH = 3.6V VIN = 2.0V, VDDH = 3.6V HIGH-level LOW-level Positive Negative Pins VDDH VDDL (*1) (*1) (*2) (*2) (*2) (*3) Symbol IDDH IDDL VIH VIL VT+ VT- VH VOH IOH = - 3mA (Type 1), - 6mA (Type 2) IOL = 3mA (Type 1), 6mA (Type 2) Condition All pins no load All pins no load VDDH = 3.6V VDDH = 3.0V Rating min - - 2.0 - 1.1 0.6 0.1 VDDH - 0.4 - -5 60 60 - - - 350 210 typ - - - - - - - - - - 120 120 - - - - max 8 550 - 0.8 2.4 1.8 - - 0.4 5 288 288 - 20 17 - - Unit mA mA V V V V V V V A k k A A A A
Pin summary
(*1) (*2) (*3) (*4) (*5) (*6) Input pins and bi-directional pins in input mode Schmitt-characteristic inputs and bi-directional pins in input mode Output pins and bi-directional pins in output mode Type 2: BCKO, BCK64O Type 1: All outputs excluding those above Inputs with pull-down resistor Inputs with pull-up resistor Input/outputs with bus hold circuit (DATA [31:0])
SEIKO NPC CORPORATION --6
SM5951A AC Characteristics VDDH = 3.0 to 3.6V, VDDL = 2.3 to 2.7V, VSS = 0V, TOPR = - 20 to 70C unless otherwise noted. When fs = 44.1kHz, the FS and BCKI clock inputs have the following frequency division relationship to the master clock input on CLK.
I
When CLK = 1024fs: (FS) cycle = 1024 x CLK cycles (BCKI) cycle [128fs mode] = 8 x CLK cycles (128fs) (BCKI) cycle [64fs mode] = 16 x CLK cycles (64fs) When CLK = 1280fs: (FS) cycle = 1280 x CLK cycles (BCKI) cycle [128fs mode] = 10 x CLK cycles (128fs) (BCKI) cycle [64fs mode] = 20 x CLK cycles (64fs)
I
System clock input
I
CLK pin
Rating Parameter Symbol min typ 11.07 (1024fs) 8.86 (1280fs) 11.07 (1024fs) 8.86 (1280fs) 22.14 (1024fs) 17.72 (1280fs) - max - - - 2 ns ns ns ns tMCWH tMCWL tMCY tr, tf 7 7 16 - Unit
HIGH-level pulsewidth LOW-level pulsewidth Pulse cycle Rise/Fall time
tMCY tMCWH tMCWL
VDDH 90% VDDH 50% VDDH 10%
CLK
tr tf
1FS clock input
I
FS pin (44.1kHz)
Rating Parameter Symbol min typ 11.34 11.34 22.68 - max - - - 10 s s s ns tFSCWH tFSCWL tFSCY tfsr, tfsf - - - - Unit
HIGH-level pulsewidth LOW-level pulsewidth Pulse cycle Rise/Fall time
tFSCY tFSCWH tFSCWL
VDDH 90% VDDH 50% VDDH 10%
FS
tfsr
tfsf
SEIKO NPC CORPORATION --7
SM5951A DSD input/output FS, BCKI, DSDIxx, EXMUTE, BCKO, BCK64O, DSDOx, DSD64Ox pins
Parameter DSD bit clock pulsewidth DSD bit clock pulse cycle DSD 64fs bit clock output pulsewidth DSD 64fs clock output pulse cycle DSD data input setup time 1 DSD data input hold time 1 DSD data input setup time 2 DSD data input hold time 2 DSD data output delay time DSD bit clock output delay time 3 Symbol tDSCW tDSCY tDS64CW tDS64CY tDSS tDSH tDSMS tDSMH tDSOD tDSCDLY Rating min 80 - - - 35 35 - 0 0 0 typ 177.16 (1/64fs) 88.58 (1/128fs) 354.31 (1/64fs) 177.16 (1/128fs) 177.16 354.31 - - - - - -
tDSCY
max - - - - - - 18 - 10 88
Unit ns ns ns ns ns ns ns ns ns ns
tDSCW
BCKI
tDSCW
tDSS
tDSH
DSDI EXMUTE
tDSMS tDSMH
1
DSDI
2
FS
tDSCDLY
tDSCY tDSCW tDSCW
BCKO
tDSOD
DSDO
1
tDSOD
tDSOD
DSDO
2
tDSCDLY tDS64CW
BCK64O
tDSOD
tDS64CY tDS64CW
DSD64O
1
tDSOD
tDSOD
DSD64O
2
1. Normal mode rating (input data setup time is referenced to the BCKI rising edge) 2. Manchester-type mode rating (input data setup time is referenced to the BCKI falling edge) 3. The delay in the state of internal synchronization relative to the FS input edge SEIKO NPC CORPORATION --8
SM5951A
MCU interface
I
ADDR [7:0], CS_X, RD_X, WR_X, DATA [31:0] pins
Parameter Symbol tACCY tADS tADH tRLW tWLW tRDZD tRDTD tRDFD tWDS tWDH Rating min 150 10 10 100 100 0 0 0 20 10 typ - - - - - - - - - - max - - - - - 20 60 10 - - Unit ns ns ns ns ns ns ns ns ns ns
Access cycle time ADDR, CS_X setup time ADDR, CS_X hold time RD_X pulsewidth WR_X pulsewidth Read data output delay time Read data defined delay time Read data output floating delay time Write data input setup time Write data input hold time

tACCY

ADDR [7:0]
CS_X
tADS tRLW tADH
RD_X
tADS tRDTD tRDZD tRDFD
tWLW
tADH
WR_X
DATA (OUT)
Hi-Z
Hi-Z
tWDS tWDH
DATA (IN)
Hi-Z
Initialization
I
RST_X pin
Parameter Symbol tINTM Rating min 6 x tMCY typ - max - Unit ns
Initialization time
VDDH tINTM
RST_X
3.0V
tINTM
SEIKO NPC CORPORATION --9
SM5951A
FUNCTIONAL DESCRIPTION
Data Input/Output Format
DSD input format The DSD input format can be set to one of 2 types by the state of SELDSDI. (1) Normal mode (SELDSDI = LOW) DSD input data is read in close to the rising edge of the bit clock BCKI. Note that even if the input is phase modulated, the data is still read in close to the rising edge of BCKI if the data is defined.
(1/64fs or 1/128fs)
BCKI
DSDI***
D1
D2
D1
D1
D2
D2
(2) Manchester-type input (SELDSDI = HIGH) DSD input data is read in during the LOW-level pulse of the bit clock BCKI.
(1/64fs or 1/128fs)
BCKI
DSDI***
D1
D1
D2
D2
Note. DSDI***: DSDI1_[3:0], DSDI2_[3:0], DSDI3_[3:0], DSDI4_[3:0], DSDI5_[3:0], DSDI6_[3:0], DSDI7_[3:0], DSDI8_[3:0] pins Note. When an external mute pattern is input on EXMUTE pin, data is read in normal mode format only, regardless of the state of SELDSDI.
SEIKO NPC CORPORATION --10
SM5951A DSD output format The DSD output format can be set to one of 2 types by the state of SELDSDO. (1) Normal mode (SELDSDO = LOW) DSD output data transitions occur on the falling edge of the bit clock BCKO.
(1/64fs or 1/128fs) BCKO BCK64O DSDO* DSD64O* D1 D2
(2) Manchester-type output (SELDSDO = HIGH) DSD output data transitions occur on the falling edge of the bit clock BCKO and then inverts on the rising edge of the bit clock BCKO.
(1/64fs or 1/128fs) BCKO BCK64O
DSDO* DSD64O* D1 D1 D2 D2
Note. DSDO*: DSDO [8:1] pins, DSD64O*: DSD64O [8:1] pins
MCU Interface
Bus access control The internal mode and coefficients can be set using either 8/16/32-bit data bus, facilitating easy connection to various kinds of MCU bus. The data bus control pins are active LOW. When the chip select (CS_X) is active, read/write control inputs are valid. When write control (WR_X) is active, data is written in on the rising edge. Data is read out when the read control (RD_X) is active.
ADDR [7:0]
CS_X
RD_X
WR_X
Hi-Z DATA [31:0] (Out) Data (Out)
Hi-Z
DATA [31:0] (In)
Hi-Z
Data (In)
Note. DATA [31:0] pins have an additional bus hold circuit which holds the previous data even when the pin is in a high-impedance ("Hi-Z") state.
SEIKO NPC CORPORATION --11
SM5951A Data bus width selection The width of the data bus for data access can be set to one of 3 types by the state of the SELBUS [1:0] pins. (1) 32-bit bus: SELBUS [1:0] = (1, x)
Micro Controller (32bit Data Bus) SM5951A
(2) 16-bit bus: SELBUS [1:0] = (0, 1)
Micro Controller (16bit Data Bus) SM5951A
(Chip_Enable) (Write_Enable) (Read_Enable)
CS_X WR_X RD_X
SELBUS1 SELBUS0
VDDH VDDH or VSS
(Chip_Enable) (Write_Enable) (Read_Enable)
CS_X WR_X RD_X
SELBUS1 SELBUS0
VSS VDDH
ADDR7 ADDR6 ADDR5 (Address) ADDR4 ADDR3 ADDR2 (VDDH or VSS) (VDDH or VSS) ADDR1 ADDR0 (VDDH or VSS) (Address)
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
(Data_Bus [31, 24]) (Data_Bus [23, 16]) (Data_Bus [15, 8]) (Data_Bus [7, 0])
DATA [31, 24] DATA [23, 16] DATA [15, 8] DATA [7, 0] (Data_Bus [15, 8]) (Data_Bus [7, 0])
(No Connect) (No Connect)
DATA [31, 24] DATA [23, 16] DATA [15, 8] DATA [7, 0]
Note. ADDR [1:0] pins are not used.
Note. ADDR0, DATA [31:16] pins are not used.
(3) 8-bit bus: SELBUS [1:0] = (0, 0)
Micro Controller (8bit Data Bus) SM5951A
(Chip_Enable) (Write_Enable) (Read_Enable)
CS_X WR_X RD_X
SELBUS1 SELBUS0
VSS VSS
ADDR7 ADDR6 ADDR5 ADDR4 (Address) ADDR3 ADDR2 ADDR1 ADDR0
(No Connect) (No Connect) (No Connect) (Data_Bus [7, 0])
DATA [31, 24] DATA [23, 16] DATA [15, 8] DATA [7, 0]
Note. DATA [31:8] pins are not used.
Internally, parameter settings and data are handled in 32-bit units, while the memory area addresses are handled in 8-bit units. For 8-bit and 16-bit access bus widths, the 2 least significant address bits (ADDR [1:0]) are used to determine which internal data bits are accessed as shown in the following table.
Internal Data bit 7-0 bit 15-8 bit 23-16 bit 31-24 bit 32-bit Access ADDR [1:0] (x, x) (x, x) (x, x) (x, x) Data Pin DATA [7:0] DATA [15:8] DATA [23:16] DATA [31:24] 16-bit Access ADDR [1:0] (0, x) (0, x) (1, x) (1, x) Data Pin DATA [7:0] DATA [15:8] DATA [7:0] DATA [15:8] 8-bit Access ADDR [1:0] (0, 0) (0, 1) (1, 0) (1, 1) Data Pin DATA [7:0] DATA [7:0] DATA [7:0] DATA [7:0]
Note. "x" in the address column are don't care bits. SEIKO NPC CORPORATION --12
SM5951A Address mapping
Address Read/ Write Initial Value 31 24 23 DATA Bit 16 15 87 Control [7] = OFFPAT [6] = DCONVEN [5:4] = DITH [1:0] [3] = DITHEN [2] = MUTESEL [1] = DSD128 [0] = SRESET [7:4] = STAT_CH2 [3:0] = STAT_CH1 [7:4] = MATCH5 [3:0] = MATCH4 [7:4] = MATCH_CH2 [3:0] = MATCH_CH1 [7] = (reserved) [6:0] = DLY_128 0
03h-00h
R/W
xxxxxx8Bh
07h-04h
R
- xx076543h - xx152B6Bh - xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h xx000000h
Switching Status [31:28] = STAT_CH8 [27:24] = STAT_CH7
0Bh-08h
R/W
[23:20] = STAT_CH6 [19:16] = STAT_CH5 Pattern Match NO. [23:20] = (reserved) [19:16] = MATCH8 [23:20] = MATCH_CH6 [19:16] = MATCH_CH5 Delay Offset [23:21] = (reserved) [20:16] = DLY_DOWN CH1 Coefficient [23:0] = CH1COEF1 [23:0] = CH1COEF2 [23:0] = CH1COEF3 [23:0] = CH1COEF4 CH2 Coefficient [23:0] = CH2COEF1 [23:0] = CH2COEF2 [23:0] = CH2COEF3 [23:0] = CH2COEF4 CH3 Coefficient [23:0] = CH3COEF1 [23:0] = CH3COEF2 [23:0] = CH3COEF3 [23:0] = CH3COEF4 CH4 Coefficient [23:0] = CH4COEF1 [23:0] = CH4COEF2 [23:0] = CH4COEF3 [23:0] = CH4COEF4 CH5 Coefficient [23:0] = CH5COEF1 [23:0] = CH5COEF2 [23:0] = CH5COEF3 [23:0] = CH5COEF4 CH6 Coefficient [23:0] = CH6COEF1 [23:0] = CH6COEF2 [23:0] = CH6COEF3 [23:0] = CH6COEF4 CH7 Coefficient [23:0] = CH7COEF1 [23:0] = CH7COEF2 [23:0] = CH7COEF3 [23:0] = CH7COEF4 CH8 Coefficient [23:0] = CH8COEF1 [23:0] = CH8COEF2 [23:0] = CH8COEF3 [23:0] = CH8COEF4
[15:12] = STAT_CH4 [11:8] = STAT_CH3 [15:12] = MATCH7 [11:8] = MATCH6 [15:12] = MATCH_CH4 [11:8] = MATCH_CH3 [15] = (reserved) [14:8] = DLY_64
0Fh-0Ch
R
Matching Status [31:28] = MATCH_CH8 [27:24] = MATCH_CH7
13h-10h 7Fh-14h 83h-80h 87h-84h 8Bh-88h 8Fh-8Ch 93h-90h 97h-94h 9Bh-98h 9Fh-9Ch A3h-A0h A7h-A4h ABh-A8h AFh-ACh B3h-B0h B7h-B4h BBh-B8h BFh-BCh C3h-C0h C7h-C4h CBh-C8h CFh-CCh D3h-D0h D7h-D4h DBh-D8h DFh-DCh E3h-E0h E7h-E4h EBh-E8h EFh-ECh F3h-F0h F7h-F4h FBh-F8h FFh-FCh
R/W - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
SEIKO NPC CORPORATION --13
SM5951A Control register The IC operating state is set by the control register.
Address 00h
I
Bit 7 OFFPAT
Bit 6 DCONVEN
Bit 5 DITH1
Bit 4 DITH0
Bit 3 DITHEN
Bit 2 MUTESEL
Bit 1 DSD128
Bit 0 SRESET
Bit 0: SRESET (default = 1) 1: State retention 0: Reset and resync When set to "0", it resets the internal computational block data and resynchronizes timing. When reset and resynchronization finishes, it is automatically set to 1 and the device is in computation mode. This bit is write-only, and reading this bit has no meaning. Bit 1: DSD128 (default = 1) 1: 128fs 0: 64fs Selects the DSD input/output sampling frequency (fs = 44.1kHz). However, the DSD64O output always has 64fs DSD sampling rate, regardless of this bit setting. Bit 2: MUTESEL (default = 0) 1: External input 0: Internal Selects the mute pattern used when mixing. The internally generated pattern is [10010110], while the external input mute pattern is entered on the EXMUTE pin. Bit 3: DITHEN (default = 1) 1: Dither ON 0: Dither OFF This applies to the dither when converting the 128fs DSD signal (DSDO*) to the 64fs DSD signal (DSD64O*). Selects dither ON/OFF. Bit [5, 4]: DITH (default = [0, 0]) [1, 1]: 1/256 [1, 0]: 1/128 [0, 1]: 1/64 [0, 0]: 1/32 This applies to the dither when converting the 128fs DSD signal (DSDO*) to the 64fs DSD signal (DSD64O*). Sets the dither level applied. Bit 6: DCONVEN (default = 0) 1: ON 0: OFF When 128fs DSD signal sampling frequency is selected, this bit selects whether down conversion to 64fs DSD signal (DSD64O*) is performed or not. Active only when DSD128 (Bit 1) is set to "1". Bit 7: OFFPAT (default = 1) 1: "96h" mute pattern 0: "H" fixed When 128fs DSD signal is not selected and down conversion is OFF, this bit selects the 64fs DSD signal (DSD64O*) output pattern. When 128fs DSD signal is selected (DSD128 is set to "1") and down conversion is ON (DCONVEN is set to "1"), this bit is inactive and the down converted 64fs DSD signal is output on DSD64O*.
I
I
I
I
I
I
Note. DSDO*: DSDO [8:1] pins, DSD64O*: DSD64O [8:1] pins
SEIKO NPC CORPORATION --14
SM5951A Switching status The following addresses are used to monitor the switching status. This area of memory is read-only.
Address 04h Address 05h Address 06h Address 07h Bit 31 Bit 23 Bit 15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STAT_CH2 [3:0] Bit 14 Bit 13 Bit 12 Bit 11
STAT_CH1 [3:0] Bit 10 Bit 9 Bit 8
STAT_CH4 [3:0] Bit 22 Bit 21 Bit 20 Bit 19
STAT_CH3 [3:0] Bit 18 Bit 17 Bit 16
STAT_CH6 [3:0] Bit 30 Bit 29 Bit 28 Bit 27
STAT_CH5 [3:0] Bit 26 Bit 25 Bit 24
STAT_CH8 [3:0]
STAT_CH7 [3:0]
The value of each address indicates the following operating status. 0 : Input DSD data is being passed directly to the output 1 : Switching from direct output (state 0) to internal computation output 4 : Internal DSM computation result signal is being output 7 to 9 : Switching from state 4 to state 0 Other : Not used Setting the number of pattern matching bits The following addresses are used to set the minimum number of matching bits in each stage of the DSD input signal switching process during mixing.
Address 08h Address 09h Address 0Ah Address 0Bh Bit 31 Bit 30 (reserved) Bit 23 Bit 15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MATCH5 [3:0] Bit 14 Bit 13 Bit 12 Bit 11
MATCH4 [3:0] Bit 10 Bit 9 Bit 8
MATCH7 [3:0] Bit 22 (reserved) Bit 29 Bit 28 Bit 27 Bit 21 Bit 20 Bit 19
MATCH6 [3:0] Bit 18 Bit 17 Bit 16
MATCH8 [3:0] Bit 26 (reserved) Bit 25 Bit 24
MATCH8 [3:0] MATCH7 [3:0] MATCH6 [3:0] MATCH5 [3:0] MATCH4 [3:0]
(Number of matching bits in 1st stage) - 1, (default = 7) (Number of matching bits in 2nd stage) - 1, (default = 6) (Number of matching bits in 3rd stage) - 1, (default = 5) (Number of matching bits in 4th stage) - 1, (default = 4) (Number of matching bits in 5th stage) - 1, (default = 3)
SEIKO NPC CORPORATION --15
SM5951A Reading the number of pattern matching bits The following addresses are used to read out the number of matching bits in each stage of the DSD input signal switching process during mixing.
Address 0Ch Address 0Dh Address 0Eh Address 0Fh Bit 31 Bit 23 Bit 15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MATCH_CH2 [3:0] Bit 14 Bit 13 Bit 12 Bit 11
MATCH_CH1 [3:0] Bit 10 Bit 9 Bit 8
MATCH_CH4 [3:0] Bit 22 Bit 21 Bit 20 Bit 19
MATCH_CH3 [3:0] Bit 18 Bit 17 Bit 16
MATCH_CH6 [3:0] Bit 30 Bit 29 Bit 28 Bit 27
MATCH_CH5 [3:0] Bit 26 Bit 25 Bit 24
MATCH_CH8 [3:0]
MATCH_CH7 [3:0]
MATCH_CH1 [3:0] MATCH_CH2 [3:0] MATCH_CH3 [3:0] MATCH_CH4 [3:0] MATCH_CH5 [3:0] MATCH_CH6 [3:0] MATCH_CH7 [3:0] MATCH_CH8 [3:0]
(Number of channel 1 matching bits) - 1 (Number of channel 2 matching bits) - 1 (Number of channel 3 matching bits) - 1 (Number of channel 4 matching bits) - 1 (Number of channel 5 matching bits) - 1 (Number of channel 6 matching bits) - 1 (Number of channel 7 matching bits) - 1 (Number of channel 8 matching bits) - 1
Output delay correction These addresses are used to set the mixing delay correction for the DSD input. The setting adjusts the time from DSD input to DSD output by an internal delay in units of the DSD rate. The actual adjustment is the value written to memory + 1.
Address 10h Address 11h Address 12h Address 13h Bit 31 Bit 7 (reserved) Bit 15 (reserved) Bit 23 Bit 22 (reserved) Bit 30 Bit 29 Bit 28 (reserved) Bit 27 Bit 21 Bit 20 Bit 14 Bit 13 Bit 12 Bit 6 Bit 5 Bit 4 Bit 3 DLY_128 [6:0] Bit 11 DLY_64 [6:0] Bit 19 Bit 18 DLY_DOWN [4:0] Bit 26 Bit 25 Bit 24 Bit 17 Bit 16 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0
DLY_128 [6:0] DLY_64 [6:0] DLY_DOWN [4:0]
(default = 107) (default = 43) (default = 21)
: Delay value when sample rate is 128fs : Delay value when sample rate is 64fs : Delay value when down sampling from DSDO (128fs) to DSD64O (64fs)
SEIKO NPC CORPORATION --16
SM5951A Coefficients The address space 80h to FFh contains 32 coefficient registers, comprising independent mixing coefficients for the 4 DSD inputs for each of the 8 channels. CHnCOEFm [23:0]: n-channel m-input coefficient (default = 0)
Coefficients are represented in linear, 2s-complement, 24-bit format. Minus coefficients have inverted polarity. Gain setting and positive/inverse (minus) polarity are represented as follows: Positive: 0dB (input level x 1.0) = 080000h Inverse : 0dB (input level x - 1.0) = F80000h
Positive maximum: 7FFFFFh (+ 24dB) Inverse maximum : 800000h (+ 24dB)
Note 1: When the gain setting is + 12dB, modulator saturation during requantization may cause noise to increase considerably. Note 2: Coefficients are read in during an interval close to the rising edge of FS (44.1kHz). If coefficient data write timing starts and/or ends in this interval, computation using written-in data can be uncertain for an interval of 1fs until it's certainly renewed at the next fetch timing. Hence, writing coefficient data during this interval should be avoided.
T = 1/44.1kHz Recommended coefficient write timing FS
Coefficient register
COFF (n)
COFF (n + 1)
Internal computation coefficient
COFF (n)
COFF (n + 1)
0.1s 1.18s Read interval (max)
SEIKO NPC CORPORATION --17
SM5951A
Mixing
(CHnCOEF1)
DSDIn_0
(CHnCOEF2)
DELAY
DSDIn_1
SWITCH
(DSD_OUTn)
(CHnCOEF3)
DSM
DSDIn_2 (SW Control) (CHnCOEF4)
DSDIn_3
(MUTE_COEF)
(Mute Pattern)
Input signal mixing This stage mixes the 4 DSD input signals on each channel. Each DSD signal is multiplied by its corresponding coefficient and then added, and the result is converted back into a 1-bit DSD signal by a modulator. The DSD input signal represents + 1.0 when HIGH and - 1.0 when LOW. If the mute pattern is selected during mixing, the muting coefficients are also multiplied and added. Coefficient interpolation and output switching The mixing coefficients are read in every 1fs cycle, and linearly interpolated for each DSD sample. The mute pattern coefficients are automatically calculated from the other input coefficients. If one of the 4 DSD input coefficients is 1.0 or - 1.0 and the other 3 input coefficients are all 0, the corresponding DSD input is switched directly to the output through a delay circuit, avoiding any signal degradation caused by the modulator. If all 4 coefficients are 0, the mute pattern path is switched and output through the delay circuit. The DSM ( modulator) bypass condition is automatically calculated from the individual coefficients. The bypass switching occurs when the DSM output matches the delayed output pattern in order to minimize noise generation.
SEIKO NPC CORPORATION --18
SM5951A
128fs 64fs Down Conversion
(DSD_OUTn) (DSDOn)
FIR Filter
DSM
(DSD64On)
The 128fs DSD output is passed through a 51-tap FIR filter that cuts high-frequency noise, then it is downsampled to 64fs. The signal is reconverted by a modulator into a 64fs DSD signal for output on DSO64On.
Synchronization
Input clock synchronization The internal computation and interface operation timing are based on the internal word clock's word boundary signal (ENFS), regardless of the BCKI input state, so that they are always synchronized. They are synchronized on the first rising edge of the word clock input on FS after initialization by pin RST_X rising edge or writing to the SRESET bit (AD = 00h) of the control register. Also, BCKI is synchronized on the first falling edge after initialization. The internal synchronization status can be monitored on pin MOSYNC. The BCKI and FS synchronization status are checked at the beginning of the word clock cycle. If synchronization is maintained for 2 consecutive word clock cycles, MOSYNC goes HIGH, with the same timing as FS, to indicate successful synchronization. MOSYNC immediately goes LOW whenever BCKI or FS lose synchronization, indicating resynchronization is required.
RST_X BCKI (BCKI Sync) FS BCKO, BCK64O (DATA Clear) MOSYNC (CLR) (ASYNC) (SYNC) (Clock Out) (ASYNC) ... (SYNC)
SEIKO NPC CORPORATION --19
SM5951A Monitoring word clock synchronization The FS input rising edge synchronization status is always monitored internally. It is monitored in a window - 2 to + 1 master clock cycles wide relative to the current synchronization timing. If the FS input rising edge occurs outside the window, an FS synchronization error occurs and resynchronization is required.
(FS Sync Error) FS CLK (Clocked FS) (ENFS)
(FS Sync OK)
(FS Sync Error)
(Internal FS Start timing) ( Internal FS Timing Watch Window )
Word Boundary Timing Monitoring input bit clock synchronization The BCKI input falling edge synchronization status is always monitored internally. It is monitored in a window - 2 to + 1 master clock cycles wide relative to the current synchronization timing. If the BCKI input falling edge occurs outside the window, a BCKI synchronization error occurs and resynchronization is required.
(BCKI Sync Error) BCKI CLK (Clocked BCKI) (Internal Bit Boundary)
(BCKI Sync OK)
(BCKI Sync Error)
(Internal Bit Count Start timing ) ( Internal Bit Timing Watch Window )
Bit Boundary Timing
SEIKO NPC CORPORATION --20
SM5951A
DSD Signal Delay Information and Adjustment
The DSD signal internal process flow is shown in the following diagram. Each stage of the process increases the data delay, and the delay is adjusted internally so that the delay is approximately 1FS cycle.
DSDIn_m
I/O Buff
MIX (1)
DSM (16)
SW (1)
Delay 128 or Delay 64
DSDOn
Delay = 18 (DSD sample) FIR Filter (26)
DSM (32)
Delay Down
DSD64On
Delay = 58 (128fs sample)
Input-stage delay (I/O buffer) The input processing delay due to DSD input format status and the BCKI/FS phase relationship is approximately 0.5 to 1.5 samples in length. (1) Normal mode timing example
Delay (MAX)
BCKI (MAX) DSDI (MAX) n+1 Delay (MIN) BCKI (MIN) DSDI (MIN) n+1
BCKI (MAX) (Clocked) BCKI (MIN) (Clocked) DSD buff1 (MAX) (Input block) DSD buff1 (MIN) (Input block) DSD buff2 [Ch8:Ch1] (Input block) CLK (1024fs)
n n-1
n+1 n
n+2 n+1
n-2
n-1
n
n+1
(ENFS)
BCKO n-1 DSD input (edit block)
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
n
n+1
CH7 CH8
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH1 CH2 CH3 CH4 CH5 CH6
COEF input (edit block)
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
SEIKO NPC CORPORATION --21
SM5951A (2) Manchester-type input mode timing example
Delay (MAX)
BCKI (MAX) DSDI (MAX) n+1 n+1 Delay (MIN) BCKI (MIN) DSDI (MIN) n+1 n+1
BCKI (MAX) (Clocked) BCKI (MIN) (Clocked) DSD buff1 (MAX) (Input block) DSD buff1 (MIN) (Input block) DSD buff2 [Ch8:Ch1] (Input block) CLK (1024fs)
n n-1
n+1 n
n+2 n+1
n-2
n-1
n
n+1
(ENFS)
BCKO n-1 DSD input (edit block)
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
n
n+1
CH7 CH8
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH1 CH2 CH3 CH4 CH5 CH6
COEF input (edit block)
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
Internal computation delay The mixing process internal data delay is determined by the DSD sampling frequency and is 18 samples in length. The down-sampled 64fs output has an additional delay of 58 samples in length at 128fs rate. Delay adjustment The internal delay immediately before output can be adjusted in units of the sample rate. The delay adjustment can be set in the following internal registers. (1) DLY_128 [6:0] (Address = 10h) (2) DLY_64 [6:0] (Address = 11h) DSDOn delay in 128fs mode DSDOn delay in 64fs mode
(3) DLY_DOWN [4:0] (Address = 12h) DSDOn DSD64On delay
SEIKO NPC CORPORATION --22
SM5951A
Initialization
After power is applied, RST_X must be held LOW for the rated time to initialize the device. During initialization, the data bus is in input mode. The output pins have the following state. DSD data outputs: LOW BCKO, BCK64O: LOW MOSYNC : LOW When RST_X goes HIGH, the synchronization adjustment takes place and internal operation commences. When the initialization is performed by software reset in SRESET (Address = 0), the coefficient registers (Addresses = 80h to FFh) are cleared, but the internal state registers (Addresses = 00h to 7Fh) maintain their current setting.
SEIKO NPC CORPORATION --23
SM5951A
Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter "Products") are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from SEIKO NPC CORPORATION (hereinafter "NPC"). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies.
SEIKO NPC CORPORATION
15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: sales@npc.co.jp
NC0319CE 2006.04
SEIKO NPC CORPORATION --24

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